Dynamic random access memories (DRAMs) consist of a plurality of memory cells respectively comprising a storage capacitor and a selection transistor. These memory cells are addressed via word and bit lines which are configured as columns and rows.
Writing into a memory cell is carried out by means of charging an associated storage capacitor with an electric charge corresponding to the respective binary data unit.
During a read operation, the stored charge is read out and amplified by means of an evaluation circuit coupled to the bit line of the memory cell. Specifically, the electric potential of the bit line is compared to the electric potential of a reference line. Depending on the potential difference, the two electric potentials are amplified to two predetermined potential values, the higher potential of the lines being in general drawn to the potential of the supply voltage and the lower potential being drawn to the ground potential.